I'm going to make some SD/xD/NAND carts (yes, I have a supply of both types of sockets ) and I'm thinking of doing a little extra IO on them. So here's a couple questions on the GPIO and NAND usage in the JB...
1) Does anyone know for sure if the state of pins 20 and 22 on the cartridge port are checked other than a single time during a cold start? (What I'm thinking is to just hook these up to weak pullups and let the CPU drive them *after* the OTP boot code has executed and control has handed off to the xD/NAND image.)
2) Has anyone tried using a 16Mx8 NAND flash device? (The only reason I ask is because I have a lot of them from back in the day and I'm planning on dual footprinting the PCB for either xD or NAND in the old Samsung TSOP-48 footprint. Specifically I have a bunch of KM29U128T's and K9F2808U0M's... Then there's some TC58256FT's and TC58128FT's, but I don't remember if they're the same footprint as the Samsung parts or not.)
My plan is to just stick a little CPLD on the cart and use GPC9 and GPC10 as control signals. Something like:
11 = SD (default)
01 = RS-232 (serial 1)
10 = CPLD
00 = [reserved for expansion]
...and then just use SPI over the 'MMC' pins to read/write the bits in the CPLD (which in turn get latched to the CPLD pins).
Basically the CPLD muxes/steers the GPIO's as necessary (or not). (So while you can use SD + xD without doing anything special, if you choose "serial" we steal "CLE" from the xD interface for SIOTxD and if you choose "CPLD" the SD clock is gated, etc.)
Now getting *at* the 'expansion IO' signals from the CPLD is a little rough in the case of an xD/SD stuffed card, but there's always a way. With an on-cart NAND there's room for a little header were the xD card would normally sit.
Any input would be appreciated.