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Vdd and TNRST
+3.3v Power and JTAG Reset Signals

New MessageVdd and TNRST (modified 0 times) bkgoodman
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Two questions:

ONE: My JTAG hardware needs a voltage source from the chip to drive the signals to the correct level (i.e. +3.3v reference). Where is a good place to get this on the JB? I have found two test points just to the north of the CPU (in the photos on the Wiki) which yeild +3.3v (these could just be logic-high outputs for all I know). I also found a test point in the NorthEast corner of the board labled "Vdd" which yields +3.3v. (There is no continuity between these points). Any idea on what the best +3.3v reference would be?

TWO: The JTAG picture labels the reset line as nTRST - I assume this means "active-low". The wiggler code also refers to this line as nTRST in the code - however - am I correct in my believe that the Wiggler *hardware* just passes this through un-inverted, and it is the JTAG program which handles the inversion? I'm asking because I have to do a bit of code for my (unsupported) JTAG cable - and It's signal is called "TRST" - i.e. no "n" - and it in fact does NOT invert the signal from the Parport. So am I correct in my believe that this is exactly as the Wiggler hardware really works?

09-10-2006 19:20:48

New MessageRE:Vdd and TNRST (modified 0 times) jbfan
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3.3V - From the component side just find the plus end of a bypass cap near where you want to pick up the voltage.
Not sure on the back side, there should be plenty of vias - the ohm meter is your friend.
For reference; pin one of the cartridge slot connector is 3.3V.

nTRST - I was originally able to use JTAG without connecting this signal. Only hooked it up later to see if it would fix an issue I was having. But yes, AFAIK it is low active.

09-11-2006 06:36:33

New MessageRE:Vdd and TNRST (modified 0 times) jbfan
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(Yeah, a longer modify timeout on messages would be nice)
am I correct in my believe that the Wiggler *hardware* just passes this through un-inverted, and it is the JTAG program which handles the inversion?
May depend on the JTAG package you are using. If you look at the schematic for the Jtager "wiggler"; there is an NPN transistor being used as an inverter on the RST line.
09-11-2006 06:52:09

New MessageRE:Vdd and TNRST (modified 0 times) bkgoodman
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Now I'm a little confused - the wiggler code below, as far as I can tell - is sending an active-low output to the pin. If the hardware inverted that - it'd be active high:

Am I mis-interpreting something?

static int
wiggler_set_trst( cable_t *cable, int trst )
{
PARAM_TRST(cable) = trst ? 1 : 0;

parport_set_data( cable->port, (PARAM_TRST(cable) ^ 1) << nTRST );
return PARAM_TRST(cable);
}

09-11-2006 08:25:32

New MessageRE:Vdd and TNRST (modified 0 times) greghol
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The following code reads: if trst is 1 then PARAM_TRST(cable) is 1 and if trst is 0 then PARAM_TRST(cable) is 0. The rest of the code mask bits and shifts it before sending it out.

PARAM_TRST(cable) = trst ? 1 : 0;

x = VarToTest ? true : false; <- The way it should be. I think that your thinking that the logical operation is the other way round. Just a guess??

Yes, the transistor is inverting the logic level so a 1 on the par port is a low on the JTAG interface nTRST.

I find that connecting nTRST only causes problems for what ever reason. This is on my Jeeni JTAG box as well as the wiggler schematic I use with various software tools. If works for you then great if not then try disconnecting it. YMMV.

09-11-2006 13:37:05

New MessageRE:Vdd and TNRST (modified 0 times) bkgoodman
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Yes - but the parport_set_data does a ^ 1 (xor) on the PARAM_TRST - inverting it.

So if you passed a "1", it would PARAM_TRST(cable) to 1.
Then the XOR would invert it to "0"
and the hardware would invert it to "1"


...so it looks like it doesn't get inverted.

Hence, my confusion...

09-12-2006 11:17:16

New MessageRE:Vdd and TNRST (modified 0 times) bkgoodman
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...maybe that's what ntrst doesn't work...
09-13-2006 06:34:43

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