This is basic analog circuit design. Actually, Q16 doen't "know" what voltage to drop - that is decided by one of the op-amps in U16. That op-amp is configured as a voltage-series feedback voltage-follower, with a reference voltage of 2.5v, and a voltage divider (from Vcore) set by a few resistors (in conjunction with SW4 on V4b/V5). The output of the op-amp drives the gate of Q16.
As long as the op-amp senses that the output voltage (Vcore) is too low, it will try to slew its output higher (driving the gate of Q16) until Q16 is driven sufficiently 'on' to make the output voltage (Vcore) high enough.
When Vcore is too high, the op-amp will try to drive Q16 'off'. This will set Vcore to exactly what the divider network and the voltage reference determine it to be.
The effect of the extra 'cooling' resistor in the drain of Q16 is merely to decrease the voltage drop across Q16, and therefore its power dissipation. This resistor could just as well be in the source of Q16, as long as the overall feedback loop (voltage divider network) senses the voltage at the Vcore pin of the CPU, rather than at the source of Q16.
We cannot use a fixed resistor (instead of Q16), because the CPU is not a constant DC load. It uses widely different currents depending on its clock speed, instruction mix, and active power-management mode. Hence the need for an active voltage regulator (U16, Q16, etc.), which can maintain a constant voltage for Vcore, regardless of the current.
