Now that I'm looking back at the archives I'm thinking that the pinouts we've been attempting to use aren't correct.
The original pinout thread is here:
http://www.linux-hacker.net/cgi-bin/UltraBoard/UltraBoard.pl?Action=ShowPost&Board=technical&Post=2013&Idle=0&Sort=0&Order=Descend&Page=0&Session=
The pinouts in the above post were based on the mappings of a Geode chip, not the Cyberblade i7. I think it was assumed that the Geode and Cyberblade chips would map and drive the pins the same way across the different modes, but I don't see the correlation here. I'm looking at the mapping from the Cyberblade specs, page 6-15, and I found the Geode specs' page 21, which was used for the original mappings, and I don't see them matching up. Someone with time and mental focus ( :) ), please doublecheck my findings in the two PDF files:
http://www.national.com/ds/CS/CS9211.pdf
http://us.f1.yahoofs.com/users/adafd72c/bc/I-Opener+Files/IOpener+DataSheets/Trident_Cyberblade_i7_cbi7.pdf?BCe4ZV_AFJNh1Cfe
If my reading comprehension is correct, this should be the correct mapping:
CN2 Pin = TFT18 Signal
1 = R5 (Red)
2 = R4
3 = R3
4 = R2
5 = VSS/GND
6 = G5 (Green)
7 = G4
8 = G3
9 = G2
10 = VSS/GND
11 = B5 (Blue)
12 = B4
13 = B3
14 = B2
15 = VSS/GND
16 = R1 (Red)
17 = R0
18 = G1 (Green)
19 = G0
20 = VSS/GND
21 = Unused/Notch (This may need to be connected; it is "DE" according to Codeman)
22 = LP/HSYNC
23 = YD/VSYNC
24 = XCLK
25 = VSS/GND
26 = VCON (Contrast Control?)
27 = DISP/ENVEE
28 = VDD/3.3v
29 = VDD/3.3v
30 = VDD/3.3v
Gwizah might be interested in hearing about this and trying it out, BTW.. I notice his first attempt was based on the original pinouts.
And if I'm smoking crack or totally missed something obvious, please let me know.

-WP