The pin being lifted connects to BD7 of the CPU. The chip is a bidirectional IO buffer that is enabled during IDE accesses by the address decoding circuitry in the SuperIO chip.
The reason the pin is lifted is that the SuperIO chip itself drives BD7 during IDE accesses. This is due to bit 7 of IDE address 0x3F7 being stolen to provide a "disk change" bit for the floppy drive interface. Because of this, the SuperIO chip must insert itself into the path for bit 7. The rest of the bits are provided by the pair of MM74HCT245 bidirectional IO buffers. So, the IDE interface of the SuperIO is as an address decoder only, except for bit 7 where it provides the data buffering/routing.
If you don't lift the pin, then both the SuperIO chip and the MM74HCT245 will drive BD7 when reading from the IDE interface. That is not a good idea.
A couple years back, another poster also stated that he didn't seem to have to lift this pin for the newer boards. Since I haven't been able to find any reason to explain why, I continue to lift that pin on both types of boards.
If you have access to a datasheet for the SuperIO chip (37c665gt or 37c666gt), you can look at the pin descriptions for
pin 22 (IDE7) and pin 17 (nDSKCHG) for more info about this. Use acrobat and search for "disk change".
You could also compare your board to the webpal schematic. I haven't been able to find any difference between the two types of boards,
other than the difference in the SuperIO chip. However, there certainly could be some.
